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| agilent technologies E2922B pci-x master target card technical overview key specifications o to 133.4 mhz clock speed 64 bit data and addressing fully pci-x compliant 53 pci-x protocol rules controllable in-system through pci-x exerciser with full capabilities, including split- transactions and 1mb data memory and real-time data generator unidirectional data path verification
agilent E2922B pci-x master target test card the E2922B pci-x master target test card provides validation engineers in the semiconductor industry a fast and predictable way to setup pci-x traffic and verify pci-x protocol compliance of first silicon. the E2922B is a dedicated validation solution for test setups where full population of all available pci-x slots is required. operated by the c-api (c application interface) through the pci-x interface itself, the E2922B can be easily integrated into existing test environments. the optionally available design verification test library offers ready to use standard tests for transaction level and data level stress tests. verification of pci-x protocol compliance the E2922B features a pci-x protocol checker, which runs constantly, checking for pci-x protocol rule violations in real-time. in total, 53 protocol rules are checked concurrently. all rules are derived from the pci-x specification. thus, just plugging the E2922B into a pci-x system and activating the protocol rule checker allows you to check for pci-x protocol compliance. the E2922B reports a list of all the errors that have occurred. each individual protocol rule can be masked. logic analyzer link the E2922B offers a connector, allowing you to connect your logic analyzer. thus, all pci-x related signals can be easily acquired using the logic analyzer. the connector is compatible with the future plus fs2104 logic analyzer link. system benefits fully programmable traffic behavior. can be easily integrated into existing test frames. predictable setup of transactional and data level test for pci-x base silicon. stresses corner cases predictably and repeatedly. over 1,000,000 test cases in less than 5 seconds. 1 in-system programmable. c-application programming interface porting support for linux, hp-ux, proprietary os and dos. system overview the E2922B is a short pci-x card, which can simply be plugged into the system under test. a customer specific c program controls the test setup. cpu ( s ) chi p se t ram e2 9 22a e2 9 22a ot h er c ard s c -ap i desi g n veri f ication test librar y customer p ro p riet y test fram e p ci-x figure 1: chip set validation using e2922a 1 1 test case @133mhz = (50 clocks delay + avg. 250 clocks for 2k bursts) *7.5ns = 2.5us. thus, 1,000,000 test cases need = 2.5s + 2s setup time. target application the E2922B targets validation labs where multiple pci-x master and targets are needed for validation, e.g. of chip-sets or high-end systems. the dedicated pci-x exercising and protocol check capabilities combined with its in-system programmability, make the E2922B the ideal test tool for the computer's core logic. predictable system and chip validation the E2922B features a fully controllable master and target (pci-x exerciser), real-time data compare and the agilent patented protocol permutation and randomizing technique. this allows engineers to validate and stress the pci-x system with specific and fully repeatable test cases. ready to use stress tests the optional available design verification test library offers a ready to use stress test, which can be fully integrated into existing test frames pci-x protocol checker the pci-x protocol checker checks 53 pci-x protocol rules in real-time (see table 1 for a detailed list). each rule can be individually masked to suppress the triggering of known problems. the rules are derived from the pci-x specification 2 , and are designed to find any possible violations of the pci-x protocol. when a protocol violation is detected, the protocol checker can: store the rule number of the first (non-masked) violated rule list all found protocol errors accumulate the number of violated rules assert the protocol violation signal on the expansion connector configuration space the agilent E2922B provides configuration space, which is fully programmable. default values (customizable) are stored in an eeprom on-board and are used to initialize the configuration space when the power is on. the configuration space can be disabled, making the card invisible to bios or o/s configuration routines. thus, analysis test is possible without having any effect on the device or the system under test. figure 2: E2922B 2 pci-x addendum to the pci local bus specification revision 1.0, september/22/1999 !" ! # ! $ $ % $ $ % !" ! # ! & ' ( & $ )* +++++ ! & $ , ! # ! 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$ 1!* & 1!* )*5 + )*%45 $ $ 1 *d7/0 " 7 < . &9 )*%45 $, 1 1 ! *& ,% " !1b,+ +$c )*%45 $ $ + ( 1 ! *& !1b,+ +$c !1b+ c )*%45 $ $ + ( 1 1 ! *& ,% " *d7/b8 c0 )*%45 $ $ + ( 1 ! *& *d7/b8 c0 *d7/b+ c0 )*%45 $ $ + ( 19:#1 & )*%45 $8 ! ,% 5!* 1!* +$ e )* + pci-x exerciser the agilent E2922B features an on-board 64 bit pci-x exerciser. the exerciser operates at 0 to 133.4 mhz, and can emulate and force practically any behavior of a pci-x device imaginable- except blatant protocol violations. the exerciser is controlled from a c-api. the exerciser features: two master queues one target four completer queues to handle independent split-transactions one requester-target handling up to 32 open requests master, target, completer and requester-target are fully programmable, operate independently of each other and are able to handle: 32/64 bit data transfers 32/64 bit addressing programmable delays between transactions block length up to 4gbyte all 14 pci-x command types architectural overview the exerciser is based on two main ideas. firstly, defining requester initiator data blocks, describing 'what' data should be transferred and secondly, defining a requester initiator behavior, describing how the transfer should be executed. for the requester initiator, up to 256 blocks of data transfers can be set up (see figure 3). in addition, requester initiator behaviors are set up, specifying how the requester initiator intends to transfer the data blocks over the pci-x bus. if any completer target replies to a transfer and requests a split transaction, the requester initiator data block attributes are moved internally to a split transaction maps for further use. the transaction map can manage up to 32 open split transactions. when completing split transactions, the requester target behaviors are used to control the transfer. the completer target behavior attributes define how the completer target of the E2922B acts. the completer target can manage up to 4 split transaction queues. it is also possible to fully control the initiation of the completion of split transactions. the completer initiator behavior attributes are used to program it. the programmable transaction scheduler decides whether completer or requester transaction is performed. all data comes or goes through the on-board data memory or from the on-board real-time data generator. requester initiator data block the requester initiator data block settings define which address space is accessed, and where data is moved. up to 256 block transfers can be defined and performed in a linear sequence by one of the two transfer queues. each block specifies: the bus command seen on c/be[3::0] in the address phase. all valid pci-x commands are supported. the 64 bit bus address the byte enable value (c/be[3::0] / c/be[4::7] the start address of the data memory or if the data generator is used the number of bytes to be transferred (1 to 4gb) if the real-time data compare for incoming data should be activated the start condition for the transfer (immediately or wait for event) the transfer queue the data is passed through s p lit tr a n s f e r ma p re q ueste r initiat or data bloc k s p lit transactio n t ar g e t mana g emen t re q uester initiat or behavi or c om p leter initiat or behavi or transa c ti o n sc he d ule r data memor y dat a com p ar e d ata g enerat or com p lete r tar g et behavi or re q ueste r tar g e t behavi or de cod e r p c i-x b us q ueue 4 q ueue 3 q ueue 2 q ueue 1 q ueue 2 q ueue 1 figure 3: E2922B pci-x exerciser architecture requester initiator behavior the requester initiator behaviors are set to specify the pci-x transfer behavior per address/data phase. up to 256 attribute entries, which can be setup as linear sequence or repeat loops, are allowed. the attributes control: 32 or 64 bit data access insertion of 1 to 65535 clock cycle delay between transactions the next data queue to be used if an automatic or customer defined tag (0..31) is used the specific burst length for the transfer ( 1 to 4096 byte) automatically rounded up to the next qword boundary the n-th adb where the requester initiator disconnects (1 to 32) perform 0 to 4 address steps how many clock cycles after the address phase req# is de-asserted (0 to 2047) how often the current transfer attributes are used (repeat value 1 to 256) latencies between the requester initiator transactions the latencies between transactions can be varied using requester initiator behavior property. the minimum latency is in general 1 clock cycle - including any sequences of read/write where real-time data compare is involved. the only exception is if the most recent transaction is a read/write transfer into data memory and the subsequent transaction is a write out of data memory. in these particular cases, the latency is 10 to 20 clock cycles. please note that it is assumed that the master does not need to disconnect before the byte count of the current sequence is transferred and that wait cycles are added if required by the pci-x specification. requester target behavior the requester behavior attributes are set to specify the pci-x transfer behavior per address/data phase if a target requests the completion of a split transaction from a requester initiator. up to 256 attribute entries, which can be setup as linear sequence or repeat loops, are allowed. the attributes control: the decode speed used (a 3 /b/c) acknowledgement of 64 bit data transfers the number of initial latency clock cycles (3 to 34) the behavior after initial latencies, either accept transfer, disconnect, signal retry or abort how often the current behavior is applied (repeat value 1 to 65536) completer target behavior attributes the completer target behavior attributes give full control over the e2928b completer target behavior, and define how the target reacts to a request. up to 256 attribute entries, which can be setup as linear sequences or repeat loops, are allowed. the attributes control: the decode speed used (a 3 /b/c) acknowledgement of 64 bit data transfers the num ber of initial latency clock cycles (0 to 31) the behavior after initial latencies, either accept transfer, signal a single data phase, retry or abort the behavior in subsequent data phases, either accept all subse- quent data phases, disconnect after 1 to 2047 data phases or abort after 1 to 2047 data phases signaling a split response, either by identifying an address value or range in the address phase, the decoder accessed, or by a subset of all 16 possible pci-x commands the split transaction queue to be used how often the current behavior is applied (repeat value 1 to 65536) configuration space and decoders in total, the E2922B features 5 decoders: one standard configuration space decoder, fully customer programmable 3 programmable target decoders (six bars) that can either hold up to 3 memory spaces (64 bit) or 2 memory spaces and 2 i/o spaces simultaneously one decoder to access the 64kbyte expansion rom all decoders can be switched off by a dip-switch on the e2929a, making the card completely invisible to the system under test. completer initiator behavior the completer behavior attributes are set to specify the pci-x transfer behavior per address/data phase if a target starts to complete a split transaction. up to 256 behavior entries, which can be setup as linear sequences or repeat loops, are allowed. the attributes control: the split transaction queue to be served the start condition for this transfer 32 or 64 bit data transfer figure 4: unidirectional data path verification 3 decode speed a is supported up to 66 mhz the number of clock cycles inserted before req# is asserted (1 to 65535) the number of clock cycles before req# is de-asserted (1 to 2047) the number of address steps ( 2 to 6) how often the current transfer attributes are used (repeat value 1 to 256) disconnect at n-th adb (2 to 63) target latencies the initial latencies can be programmed with the completer target behavior attributes. depending on the selected decode speed and address phases, the test card automatically adds the needed number of wait states to achieve the defined initial latency. a minimum of one wait cycles is always added when using decode speed b, c, minimum two wait cycles are needed with decode speed a. in case the subsequent target access is a 'read from target' and the most recent event was a 'write to target', 'read from other target address', 'master write' or 'master read', the minimum initial latency is 15 clock cycles. data memory the E2922B features a 1mb (128k x 2 dwords) programmable read/write data memory. master / requester and target/ completer share the memory. the address decoders can selectively address it. the data memory can: store data from read/write transfers be mapped to any pci-x address space data generator !" the generator features the following patterns: walking ones or zeros ground bounce count up (unique data) pseudo random pattern (unique data) the count up and pseudo random pattern are unique up to the length of 1m quad words (4mb). the data uniqueness is derived out of the lower bit 2 to 22 of the bus address. real-time data compare real-time data compare can be performed either on: memory: when data is written to the memory it is compared against the actual memory content data generator : based on the data address, the generator calculates the expected data and compares it with incoming data. c-api / ppr the E2922B comes with a c- application programming interface (c-api) which provides a programming interface for setting up and controlling the master target card. the test program must run on the system-under-test itself. the pci-x interface itself is used to control the card. the library functions are divided into groups, which allow you to set up and control the various capabilities of the agilent E2922B. recommended development environment: ms visual c++ v. 6.0 or higher. protocol permutation and randomization (ppr) # $ % & ' # $ ' ' ' ' ' ' & generating permutations by specifying lists of protocol variations, which must occur, the user-defined protocol constraints can be easily set. for example, which different burst lengths, wait cycles, memory read/write commands, etc. then, ppr automatically moves simultaneously through the lists. with each step, that is, with each permutation, the next value in this list is combined with the next values in the other lists. the hardware based permutation proceeds in this way until each value of each list is combined with all values of the other list, and thus all combinations are covered. in this way, the repetition or omission of combinations is avoided. documented test coverage % ' ' optimized test time the values to be varied can be specified for each master and target attribute separately. thus, focusing on interesting cases can optimize testing time. by carrying out these protocol permutations in real-time within the exerciser hardware, these tests run much more quickly than any other cpu-based test program. effective test generation the exhaustive c-library makes it simple to focus on test structuring, partitioning and the specification of protocol constraints. this means that an appropriate and valuable test for protocol verification with meaningful results can quickly be obtained. once started, the test can easily be extended to incorporate newly gained experiences or to address testing needs of newly invented pci-x features. deterministic test conditions in contrast to pci-x traffic generated by other pci-x cards, the generated variations are completely deterministic and reproducible. supported protocol variations the exerciser and analyzer allows the variation constraints for the pci-x transfer, pci-x master/requester and pci-x target/completer behavior to be specified. all specified constraints can be permutated against each other and up to 100 constraints can be maintained per list. pci-x transfer variations the generator features the following algorithms: start address alignment; a list of arbitrary address alignments to start pci-x transfers at given offsets (e.g. 1 dword) relative to the qword boundaries byte enables; a list of selected values for the c/be lines during the address phase block size; a block describes a contiguous range in memory available to be transferred. a list of up to 100 different block sizes (from 1 to 4096 byte) can be selected to be transferred bus commands; a list of selected pci-x bus commands. all selected commands are permutated with other selected constraints, as appropriate, for the specified transfer direction and pci-x specifications permutation of release ordering bit permutation of no snoop bit target behavior variations the requester initiator allows for the variation of: byte count (1 to 4096) disconnect/initiator termination delay address stepping req64 release req the completer initiator allows for the variation of: error message, yes/no partitioning delay address stepping req64 release req general specifications pci-x specifications: pci-x bus: 32/64 bit addressing: 32/64 bit pci clock range: exerciser: 0 to 133.4 mhz +3 8 $ ' ( $ f %g* hg* the e2922a fully meets timing specifications for 133 mhz pci-x. electrical specifications: for 3.3v environment, complies with pci-x spec. 1.0. decoupling: unused 3.3 v power pins are decoupled. power requirements: consumes less than 25 w from pci-x slot. trace length limits: meets pci-x specifications. signal loading: less than 10 pf, fully pci-x compliant. operating temperature: -40c to +55c. mechanical dimensions: short card, occupying one slot. ordering information E2922B pci-x master target test card includes: 32/64 bit, 0..133.4 mhz pci-x protocol checker on-board 32/64 bit, 0..133 mhz exerciser hardware ppr hardware c-api including drivers for windows nt software media cd when ordering without base product, s/n of the existing E2922B must be notified on purchase order. porting support is available to port c- api to linux, hp-ux or proprietary operating systems. contact your local sales offices for detailed information. accessories futureplus analysis probe 4 fs2104 for connection of the agilent logic analyzer. available from agilent as resell part fsi 60042 4 the analysis probe is not an agilent product. agilent works closely with future plus to ensure quality products, but the vendor is responsible for functionality, pre-sales and post sales support and warranty. pci analyzer -protocol checker - 64k state pci logic analyzer -4mb fast host interface - timing checker -real-time performance measures -gui - rs-232 interface e2940a compact pci 32/64 bit 66mhz e2925b pci 32 bit 33 mhz e2928a pci 32/64 bit 66 mhz e2929b pci-x 32/64 bit 133 mhz -protocol checker -rs-232/usb interface - gui opt.100 pci-x analyzer - 2m state pci logic analyzer -4mb fast host interface -real- time performance measures - gui opt.200 pci performance optimizer 4m trace memory recommended please order separately 32/64 bit 66 mhz pci-x performance optimizer -post processed and real-time performance analyzer - performance report - gui opt.300 pci exerciser - master and target -gui - cli -512 kb on-board memory 32/64 bit 33 mhz 32 bit 33 mhz 32/64 bit 66 mhz pci-x exerciser - master - target - gui - 1mb onboard data memory opt. 310 system validation package - peer-to-peer test -system memory test - system load test - protocol load test - protocol check - gui opt.320 c-api/ppr - c-programming interface library -protocol permutation and randomization library overview pci/pci-x e2920 series pci-pci-x bundle: with the e2997a agilent aslo offers a great price on the purchase of the e2928a pci card and the e2929b pci-x card. master target test card the E2922B pci-x master target test card provides validation engineers in the semiconductor industry a fast and predictable way to set up pci-x protocl compliance of first silicon. ! " agilent technologies' test and measurement support, services, and assistance agilent technologies aims to maximize the value you receive, while minimizing your risk and problems. we strive to ensure that you get the test and measurement capabilities you paid for and obtain the support you need. our extensive support resources and services can help you choose the right agilent products for your applications and apply them successfully. every instrument and system we sell has a global warranty. support is available for at least five years beyond the production life of the product. two concepts underlay agilent's overall support policy: "our promise" and "your advantage." our promise our promise means your agilent test and measurement equipment will meet its advertised performance and functionality. when you are choosing new equipment, we will help you with product information, including realistic performance specifications and practical recommendations from experienced test engineers. when you use agilent equipment, we can verify that it works properly, help with product operation, and provide basic measurement assistance for the use of specified capabilities, at no extra cost upon request. many self-help tools are available. your advantage your advantage means that agilent offers a wide range of additional expert test and measurement services, which you can purchase according to your unique technical and business needs. solve problems efficiently and gain a competitive edge by contracting with us for calibration, extra-cost upgrades, out-of-warranty repairs, and on-site education and training, as well as design, system integration, project management, and other professional services. experienced agilent engineers and technicians worldwide can help you maximize your productivity, optimize the return on investment of your agilent instruments and systems, and obtain dependable measurement accuracy for the life of those products. related agilent literature agilent e2925b 32bit, 33 mhz, pci exerciser & analyzer, technical specifications, p/n 5968-3501e agilent e2928a 32/64bit, 66 mhz, pci exerciser & analyzer, technical specifications, p/n 5968-3506e agilent e2940a compactpci exerciser & analyzer, technical specifications, p/n 5968-1915e agilent e2929b pci-x exerciser & analyzer, technical overview, p/n 5968-8984e agilent system validation pack, agilent system test library, technical overview, p/n 5968-3500e agilent e2920 computer verification tools, pci series, brochure, p/n 5968-9694e intel discusses basic concepts of pci performance and efficient use of pci with the agilent e2920 series, case stuy, p/n 5988-0488e hp nsd stabilizes server designs quickly and completely with the agilent e2920 pci series, case study, p/n 5968-6948e hp hstc speeds high-end server testing and reduces engineering costs with the agilent e2920 pci series, case study, p/n 5968-6949e agilent e2920 verification tools, pci series gives altera corporation competitive advantage, case study, p/n 5968-4191e you can find the current literature and software at: www.agilent.com/find/pci_products for more information, please visit us at: www.agilent.com/find/pci_overview by internet, phone, or fax, get assistance with all your test & measurement needs online assistance: www.agilent.com/find/assist phone or fax united states: (tel) 1 800 452 4844 canada: (tel) 1 877 894 4414 (fax) (905) 206 4120 europe: (tel) (31 20) 547 2000 japan: (tel) (81) 426 56 7832 (fax) (81) 426 56 7840 latin america: (tel) (305) 267 4245 (fax) (305) 267 4286 australia: (tel) 1 800 629 485 (fax) (61 3) 9272 0749 new zealand: (tel) 0 800 738 378 (fax) 64 4 495 8950 asia pacific: (tel) (852) 3197 7777 (fax) (852) 2506 9284 product specifications and descriptions in this document subject to change without notice. copyright ( 2000 agilent technologies printed in germany july 02 2002 5968-9577e |
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